Table of Contents
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Introduction
1.3
Configurable options
1.3.1
Interrupts
1.3.2
MPU
1.3.3
ETM
1-12
This section shows the configuration options for the processor. Contact your
implementor to confirm the configuration of your implementation.
The number of external interrupts can be configured at implementation from 1 to 240.
The number of bits of interrupt priority can be configured at implementation from three
to eight bits.
The Cortex-M3 system can be configured at implementation to include an MPU.
Chapter 9 Memory Protection Unit describes the MPU.
The Cortex-M3 system can be configured at implementation to include an ETM.
Chapter 16 Embedded Trace Macrocell Interface describes the ETM.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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