Figure 12-18 Sw-Dp Idle Timing - ARM Cortex-M3 Technical Reference Manual

Debug Port
12-40
Figure 12-18 shows a sequence of transfers separated by IDLE periods. It shows that
the wire is always handed back to the host after any transfer.
After the last bit in a packet, the line can be LOW, or idle, for any period longer than a
single bit, to enable the Start bit to be detected for back-to-back transactions.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Figure 12-18 SW-DP idle timing

ARM DDI 0337B