Activation Levels; Table 5-13 Privilege And Stack Of Different Activation Levels; Table 5-14 Exception Transitions - ARM Cortex-M3 Technical Reference Manual

Exceptions
5.13

Activation levels

Active Exception
Reset
a b
ISR or NMI
Fault:
Hard fault
Bus fault
c
No CP fault
Undefined instruction fault
Debug monitor
d
SVC
External interrupt
a. Interrupt service routine.
b. Nonmaskable interrupt.
c. Coprocessor.
d. Software interrupt.
5-32
When no exceptions are active, the processor is in Thread mode. When an ISR or fault
handler is active, the processor enters Handler mode. Table 5-13 lists the privilege and
stacks of the activation levels.
Active exception Activation level
None Thread mode
ISR active Asynchronous pre-emption level
Fault handler active Synchronous pre-emption level
Reset Thread mode
Table 5-14 summarizes the transition rules for all exception types and how they relate
to the access rules and stack model.
Triggering event
Reset signal
Set-pending software instruction or
hardware signal
Escalation
Memory access error
Absent CP access
Undefined instruction
Debug event when halting not enabled
SVC instruction
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Table 5-13 Privilege and stack of different activation levels

Transition type
Thread
Asynchronous
pre-emption
Synchronous
pre-emption
Synchronous
Non-Confidential
Privilege Stack
Privileged or user Main or process
Privileged Main
Privileged Main
Privileged Main

Table 5-14 Exception transitions

Privilege
Privileged
or user
Privileged
Privileged
Privileged
ARM DDI 0337G
Unrestricted Access
Stack
Main or
process
Main
Main
Main