Table 3-10 Etm Registers - ARM Cortex-M3 Technical Reference Manual

3.1.7 Embedded Trace Macrocell registers
Name
ETM Control
Configuration Code
Trigger event
ASIC Control
ETM Status
System Configuration
TraceEnable
TraceEnable Event
TraceEnable Control 1
FIFOFULL Region
FIFOFULL Level
ViewData
Address Comparators
Counters
ARM DDI 0337G
Unrestricted Access
Name of register
PID3
CID0
CID1
CID2
CID3
Table 3-10 gives a summary of the Embedded Trace Macrocell (ETM) registers. For a
detailed description of the ETM registers, see Chapter 14 Embedded Trace Macrocell.
Type
Read/write
Read-only
Write-only
Write-only
Read-only or read/write
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only or read/write
Write-only
Write-only
Write-only
Copyright © 2005-2008 ARM Limited. All rights reserved.
Address
0xE0041000
0xE0041004
0xE0041008
0xE004100C
0xE0041010
0xE0041014
0xE0041018
0xE0041020
0xE0041024
0xE0041028
0xE004102C
0xE0041030-0xE004103C
0xE0041040- 0xE004113C
0xE0041140-0xE004157C
Non-Confidential
Table 3-9 TPIU registers (continued)
Type Address
Read only
0xE0040FEC
Read only
0xE0040FF0
Read only
0xE0040FF4
Read only
0xE0040FF8
Read only
0xE0040FFC

Table 3-10 ETM registers

,
0xE004101C
System Control
Reset value
0x00
0x0D
0x90
0x05
0xB1
Present
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
No
No
No
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