Table 13-2 Atb Port Signals - ARM Cortex-M3 Technical Reference Manual

Trace Port Interface Unit
Name
TRACECLK
TRACEDATA[3:0]
SWV
Name Type
CLK Input
nRESET Input
CLKEN Input
ATVALID1S Input
ATREADY1S Output
ATDATA1S[7:0] Input
ATID1S[6:0] Input
ATVALID2S Input
ATREADY2 Output
ATDATA2S[7:0] Input
ATID2S[6:0] Input
13-6
Type Description
Output TRACEDATA changes on both edges of TRACECLK.
Output Output data for clocked modes.
Output Output data for asynchronous modes.
ATB interface
There is one or two ATB interfaces depending on the TPIU configuration. Table 13-2
describes the ATB Port signals. The signals for port 2 are not used when the TPIU is
configured with a single ATB interface.
Description
Trace bus and APB interface clock.
Reset for the CLK domain (ATB/APB interface).
Clock enable for CLK domain.
Data from trace source 1 is valid in this cycle.
If this signal is asserted (ATVALID high), then the data was accepted this cycle from
trace source 1.
Trace data input from source 1.
Trace source ID for source 1. This must not change dynamically.
Data from trace source 2 is valid in this cycle.
If this signal is asserted (ATVALID high), then the data was accepted this cycle from
trace source 2.
Trace data input from source 2.
Trace source ID for source 2. This must not change dynamically.
Miscellaneous configuration inputs
Table 13-3 on page 13-7 describes the miscellaneous configuration inputs.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 13-1 Trace Out Port signals

Table 13-2 ATB Port signals

ARM DDI 0337B