Table 5-11 Debug Faults - ARM Cortex-M3 Technical Reference Manual

Exceptions
Fault Flag
Internal halt request HALTED
Breakpoint BKPT
Watchpoint DWTTRAP
External EXTERNAL
Vector catch VCATCH
5.12.3 Fault status registers and fault address registers
5-30
Table 5-11 shows debug faults.
Notes
NVIC request from, for example, step, core halt
SW breakpoint from patched instruction or FPB
Watchpoint match in DWT
EDBGRQ line asserted
Vector catch triggered. Corresponding FSR contains the
primary cause of the exception.
Each fault has a fault status register with a flag for that fault.
There are:
• three configurable fault status registers that correspond to the three configurable
fault handlers
• one hard fault status register
• one debug fault status register.
Depending on the cause, one of the five status registers has a bit set.
There are two Fault Address Registers (FAR):
• Bus Fault Address Register (BFAR)
• Memory Fault Address Register (MFAR).
A flag in the corresponding fault status register indicates when the address in the fault
address register is valid.
Note
BFAR and MFAR are the same physical register. Because of this, the BFARVALID and
MFARVALID bits are mutually exclusive.
Table 5-12 on page 5-31 shows the fault status registers and two fault address registers.
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Table 5-11 Debug faults

Trap enable bit
-
-
-
-
VC_xxx bit(s) or
RESETVCATCH set
ARM DDI 0337G
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