Table 17-11 Integration Test Register-Itatbctr0 Bit Assignments; Figure 17-9 Integration Test Register-Itatbctr0 Bit Assignments; Figure 17-10 Integration Mode Control Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Trace Port Interface Unit
31
Bits Field
[31:1] -
[0] ATVALID1, ATVALID2
31
17-16
Figure 17-9 shows the bit assignments of the Integration Test Register bit assignments.

Figure 17-9 Integration Test Register-ITATBCTR0 bit assignments

Table 17-11 describes the bit assignments of the Integration Test Register bit
assignments.

Table 17-11 Integration Test Register-ITATBCTR0 bit assignments

Function
Reserved
This bit reads or sets the value of ATVALIDS1 OR-ed with ATVALIDS2.
Integration Mode Control Register
The Integration Mode Control Register enables topology detection.
The register address, access type, and Reset state are:
Address 0xE0040F00
Access Read/write
Reset state
0x0
Figure 17-10 shows the bit assignments of the Integration Mode Control Register.

Figure 17-10 Integration Mode Control Register bit assignments

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Reserved
SBZ
1
ATVALID1
ATVALID2
2 1
FIFO test mode
Integration test mode
ARM DDI 0337G
0
0