Figure 5-7 Pre-Emption Flowchart - ARM Cortex-M3 Technical Reference Manual

5.14.2 Pre-emption
5.14.3 Return
ARM DDI 0337G
Unrestricted Access
Figure 5-7 shows what happens when an exception pre-empts the current ISR.
Read new PC from vector table
Yes
Yes
Figure 5-8 on page 5-36 shows how the processor restores the stacked ISR or tail-chains
to a late-arriving interrupt with higher priority than the stacked ISR.
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I bus
Late-arriving
interrupt?
No
Fill pipeline at PC
Late-arriving
interrupt?
No
Non-Confidential
Pre-empt
D bus
Push registers r0-r3, r12, LR,
PC, and xPSR onto SP stack
Execute instructions

Figure 5-7 Pre-emption flowchart

Exceptions
Synchronize
5-35