Table 12-18 Control/Status Register Bit Assignments; Figure 12-22 Control/Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Debug Port
Bits Access Function
[31] RO CSYSPWRUPACK
[30] R/W CSYSPWRUPREQ
[29] RO CDBGPWRUPACK
[28] R/W CDBGPWRUPREQ
[27] RO CDBGRSTACK
[26] R/W CDBGRSTREQ
[25:24] - -
[21:12] R/W TRNCNT
12-54
It is a read-write register, in which some bits have different access rights. It is
Implementation-defined whether some fields in the register are supported, and
Table 12-18 shows which fields are required in all implementations.
Figure 12-22 shows the register bit assignments.
Table 12-18 lists the bit functions of the Control/Status Register.
Description
System power-up acknowledge.
System power-up request.
After a reset this bit is Low (0).
Debug power-up acknowledge.
Debug power-up request.
After a reset this bit is Low (0).
Debug reset acknowledge.
Debug reset request.
After a reset this bit is Low (0).
Reserved, RAZ/SBZP
Transaction counter.
After a reset the value of this field is Unpredictable.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Figure 12-22 Control/Status Register bit assignments

Table 12-18 Control/Status Register bit assignments

Required?
No
No
No
No
Yes
Yes
Yes
ARM DDI 0337B