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11.2
System Debug Access
ARM DDI 0337B
Debug control and data access occurs through the AHB-AP interface. This interface is
driven by either the SW-DP or JTAG-DP components. See Chapter 12 Debug Port for
information on the SW-DP and JTAG-DP components. Access includes:
•
The internal Private Peripheral Bus (PPB). Through this bus, the debugger can
access Cortex-M3 components, including:
—
Nested Vectored Interrupt Controller (NVIC). Debug access to the
processor core is made through the NVIC. For details, see Chapter 10 Core
Debug.
—
Data Watchpoint and Trace (DWT) unit.
—
Flash Patch and Breakpoint (FPB) unit.
—
Instrumentation Trace Macrocell (ITM).
—
Memory Protection Unit (MPU).
•
The External Private Peripheral Bus. Through this bus, debug access can be made
to:
—
Embedded Trace Macrocell (ETM). A low-cost trace macrocell that
supports instruction trace only. See Chapter 15 Embedded Trace Macrocell
for more information.
—
Trace Port Interface Unit (TPIU). This component acts as a bridge between
the Cortex-M3 trace data (from the ITM, and ETM if present) and an
off-chip Trace Port Analyzer. See Chapter 13 Trace Port Interface Unit for
more information.
—
ROM table.
•
The DCode bus. Through this bus, debug can access memory located in code
space.
•
The System bus. Through this bus, memory and peripherals located in system bus
space can be accessed.
Figure 11-1 on page 11-4 shows the structure of the system debug access, and shows
how each of the system components and external buses can be accessed using the
AHB-AP.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
System Debug
11-3
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