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Memory Map
Code
SRAM
SRAM_bitband
Peripheral
Periph_bitband
External RAM
External Device
Private Peripheral Bus
System
ARM DDI 0337G
Unrestricted Access
Table 4-1 shows the processor interfaces that are addressed by the different memory
map regions
Interface
Instruction fetches are performed over the ICode bus. Data accesses are performed over the
DCode bus.
Instruction fetches and data accesses are performed over the system bus.
Alias region. Data accesses are aliases. Instruction accesses are not aliases.
Instruction fetches and data accesses are performed over the system bus.
Alias region. Data accesses are aliases. Instruction accesses are not aliases.
Instruction fetches and data accesses are performed over the system bus.
Instruction fetches and data accesses are performed over the system bus.
Accesses to:
•
Instrumentation Trace Macrocell (ITM)
•
Nested Vectored Interrupt Controller (NVIC)
•
Flashpatch and Breakpoint (FPB)
•
Data Watchpoint and Trace (DWT)
•
Memory Protection Unit (MPU)
are performed to the processor internal Private Peripheral Bus (PPB).
Accesses to:
•
Trace Point Interface Unit (TPIU)
•
Embedded Trace Macrocell (ETM)
•
System areas of the PPB memory map
are performed over the external PPB interface.
This memory region is Execute Never (XN), and so instruction fetches are prohibited. An MPU,
if present, cannot change this.
System segment for vendor system peripherals. This memory region is XN, and so instruction
fetches are prohibited. An MPU, if present, cannot change this.
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Memory Map
Table 4-1 Memory interfaces
4-3
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