Branch Status Interface; Table 15-2 Branch Status Signal Function - ARM Cortex-M3 Technical Reference Manual

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Embedded Trace Macrocell Interface
15.3

Branch status interface

Name
Direction
BRCHSTAT
Output
15-6
The processor speculatively fetches some branch targets at decode time rather than
waiting for the branch to be executed. Because the processor has an internal pre-fetch
buffer, incorrect speculative fetches might not incur a penalty depending on the
instructions being executed and the number of wait-states on the memory. This means
that branches for low wait state memories can be executed in one cycle. Certain
implementations might find it beneficial to employ additional pre-fetching logic
external to the processor to improve instruction throughput. This logic might be able to
use BRCHSTAT to improve efficiency. The branch status signal, BRCHSTAT, gives
information about the opcode currently in decode. BRCHSTAT indicates whether the
current instruction in decode causes a non-sequential fetch to occur at decode time or
execute time, whether the branch is conditional and whether the branch is forward or
backwards. Execute time branches might have multicycle BRCHSTAT, which is
dependent on the stall of the preceding opcode in execute. Table 15-2 describes the
signal function.
Description
0000 = No branch currently in decode
0001 = Decode time conditional branch backwards currently in decode
0010 = Decode time conditional branch currently in decode
0011 = Execute time conditional branch currently in decode
0100 = Decode time unconditional branch currently in decode
0101 = Execute time unconditional branch in decode
0110 = Reserved
0111 = Reserved
1000 = Conditional branch in decode taken, cycle after b0001 or b0010
Table 15-3 on page 15-7 shows the branches that the processor can execute. For each
type of branch the stage in which the branch is evaluated is shown. For example, all
branches with immediates are evaluated during decode. This means that when ever a
branch immediate enters the decode stage the branch target address is issued on the
AHB.
Copyright © 2005-2008 ARM Limited. All rights reserved.

Table 15-2 Branch status signal function

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ARM DDI 0337G
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