Table 17-6 Async Clock Prescaler Register Bit Assignments; Figure 17-3 Supported Sync Port Size Register Bit Assignments; Figure 17-4 Async Clock Prescaler Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Trace Port Interface Unit
31
31
17-10
Figure 17-3 shows the bit assignments.

Figure 17-3 Supported Sync Port Size Register bit assignments

Current Sync Port Size Register
This register is read/write. The Current Sync Port Size Register has the same format as
the Supported Sync Port Sizes Register but only one bit is set, and all others must be
zero. Writing values with more than one bit set, or setting a bit that is not indicated as
supported is not supported and causes Unpredictable behavior.
It is more convenient to use the same format as the Supported Sync Port Sizes Register
because it saves on having to decode the sizes later on in the device, and also maintains
the format from the other register bank for checking for valid assignments.
On reset this defaults to the smallest possible port size, 1 bit, and so reads as
Async Clock Prescaler Register
Use the Async Clock Prescaler Register to scale the baud rate of the asynchronous
output.
Figure 17-4 shows the bit assignments of the Async Clock Prescaler Register.
Reserved

Figure 17-4 Async Clock Prescaler Register bit assignments

Table 17-6 describes the bit assignments of the Async Clock Prescaler Register.
Bits
[31:13]
[12:0]
Copyright © 2005-2008 ARM Limited. All rights reserved.
Reserved
13

Table 17-6 Async Clock Prescaler Register bit assignments

Field Function
- Reserved. RAZ/SBZP.
PRESCALER Divisor for TRACECLKIN is Prescaler + 1.
12
PRESCALER
ARM DDI 0337G
3 2 1 0
04 03 02 01
.
0x00000001
0