Table 11-9 Dwt Cpi Count Register Bit Assignments; Table 11-10 Dwt Exception Overhead Count Register Bit Assignments; Figure 11-7 Dwt Exception Overhead Count Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Field Name Definition
[31:8] - Reserved.
[7:0] CPICNT Current CPI counter value. Increments on the additional cycles (the first cycle is not counted)
required to execute all instructions except those recorded by DWT_LSUCNT. This counter also
increments on all instruction fetch stalls.
If CPIEVTENA is set, an event is emitted when the counter overflows.
Clears to 0 on enabling.
Field Name Definition
[31:8] - Reserved.
[7:0] EXCCNT Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for
example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow
(every 256 cycles). This counter initializes to 0 when enabled.
Clears to 0 on enabling.
ARM DDI 0337B
Table 11-9 describes the fields of the DWT CPI Count Register.
DWT Exception Overhead Count Register
Use the DWT Exception Overhead Count Register to count the total cycles spent in
interrupt processing.
The register address, access type, and Reset state are:
Address
0xE000100C
Access Read-write
Reset state
-
Figure 11-7 shows the fields of the DTW Exception Overhead Count Register.

Figure 11-7 DWT Exception Overhead Count Register bit assignments

Table 11-10 describes the fields of the DWT Exception Overhead Count Register.

Table 11-10 DWT Exception Overhead Count Register bit assignments

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Table 11-9 DWT CPI Count Register bit assignments

System Debug
11-19