Table 3-6 Ahb-Ap Register Summary - ARM Cortex-M3 Technical Reference Manual

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System Control
Name
Control and Status
Word (CSW)
Transfer Address
(TAR)
Data Read/write
(DRW)
Banked Data 0
(BD0)
Banked Data 1
(BD1)
Banked Data 2
(BD2)
Banked Data 3
(BD3)
Debug ROM
Address
Identification
Register (IDR)
3-10
AHB-AP registers
Table 3-6 gives a summary of the Advanced High Performance Bus Access Port
(AHB-AP) registers. For a detailed description of the AHB-AP registers, see Chapter 11
System Debug.
Type
Address
Read/write
0x00
Read/write
0x04
Read/write
0x0C
Read/write
0x10
Read/write
0x14
Read/write
0x18
Read/write
0x1C
Read only
0xF8
Read only
0xFC
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 3-6 AHB-AP register summary

Reset
Description
value
See Register
AHB-AP Control and Status Word Register
AHB-AP Transfer Address Register
0x00000000
AHB-AP Data Read/Write Register
-
-
AHB-AP Banked Data Registers
-
AHB-AP Banked Data Registers
-
AHB-AP Banked Data Registers
-
AHB-AP Banked Data Registers
0xE000E000
AHB-AP Debug ROM Address Register
AHB-AP ID Register
0x04770011
ARM DDI 0337B

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