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Nested Vectored Interrupt Controller
Bits
Field
[31:5]
-
[4]
SEVONPEND
[3]
-
[2]
SLEEPDEEP
[1]
SLEEPONEXIT
[0]
-
8-26
Table 8-18 describes the bit assignments of the System Control Register.
Function
Reserved.
When enabled, this causes WFE to wake up when an interrupt moves from inactive to
pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction
generated. The event input, RXEV, is registered even when not waiting for an event, and so
effects the next WFE.
Reserved.
Sleep deep bit:
1 = indicates to the system that Cortex-M3 clock can be stopped. Setting this bit causes the
SLEEPDEEP port to be asserted when the processor can be stopped.
0 = not OK to turn off system clock.
For more information about the use of SLEEPDEEP, see Chapter 7 Power Management.
Sleep on exit when returning from Handler mode to Thread mode:
1 = sleep on ISR exit.
0 = do not sleep when returning to Thread mode.
Enables interrupt driven applications to avoid returning to empty main application.
Reserved.
Configuration Control Register
Use the Configuration Control Register to:
•
enable NMI, Hard Fault and FAULTMASK to ignore bus fault
•
trap divide by zero, and unaligned accesses
•
enable user access to the Software Trigger Exception Register
•
control entry to Thread Mode.
The register address, access type, and Reset state are:
Address
0xE000ED14
Access
Read/write
Reset state
0x00000200
Note
STKALIGN can be reset to 0 or 1 depending on the value of STKALIGNINIT.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Table 8-18 System Control Register bit assignments
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ARM DDI 0337G
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