Table 13-8 Integration Test Register Bit Assignments; Figure 13-7 Integration Test Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Trace Port Interface Unit
13-12
The register address, access type, and Reset state are:
Address
0xE0040308
Access Read only
Reset state
0x00
Integration Test Registers
Use the Integration Test Registers to perform topology detection of the TPIU with other
devices in a Cortex-M3 system. These registers enable direct control of outputs and the
ability to read the value of inputs. The processor provides two Integration Test
Registers:
• Integration Test Register - ITATBCTR2
• Integration Test Register - ITATBCTR0.
Integration Test Register-ITATBCTR2
The register address, access type, and Reset state are:
Address
0xE0040EF0
Access Read only
Reset state
0x0
Figure 13-7 shows the fields of the Integration Test Register bit assignments.
Table 13-8 describes the fields of the Integration Test Register bit assignments.
Field Name
[31:1] -
[0] ATREADY1
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Figure 13-7 Integration Test Register bit assignments

Table 13-8 Integration Test Register bit assignments

Definition
Reserved
This bit reads or sets the value of ATREADYS1 and ATREADYS2.
ARM DDI 0337B