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10.2
Core debug registers
10.2.1
Debug Halting Control and Status Register
ARM DDI 0337G
Unrestricted Access
The registers that provide debug operations are:
•
Debug Halting Control and Status Register
•
Debug Exception and Monitor Control Register on page 10-8.
•
Debug Core Register Data Register on page 10-8
•
Debug Exception and Monitor Control Register on page 10-8.
The purpose of the Debug Halting Control and Status Register (DHCSR) is to:
•
provide status information about the state of the processor
•
enable core debug
•
halt and step the processor.
The DHCSR:
•
is a 32-bit read/write register
•
address is
0xE000EDF0
Note
The DHCSR is only reset from a system reset, including power on. Bit 16 of DHCSR
is Unpredictable on reset.
Figure 10-1 on page 10-4 shows the bit assignments in the register.
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.
Non-Confidential
Core Debug
10-3
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