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16.2
CPU AHB trace macrocell interface port descriptions
Port name
HTMDHADDR[31:0]
HTMDHTRANS[1:0]
HTMDHSIZE[1:0]
HTMDHBURST[2:0]
HTMDHPROT[3:0]
HTMDHWDATA[31:0]
HTMDHWRITE
HTMDHRDATA[31:0]
HTMDHREADY
HTMDHRESP[1:0]
HTMDHADDR[31:0]
HTMDHTRANS[1:0]
ARM DDI 0337G
Unrestricted Access
Table 16-1 list the AHB interface ports.
Direction
Description
Output
32-bit address.
Output
Output indicates the type of the current data transfer. Can be IDLE,
NONSEQUENTIAL, OR SEQUENTIAL.
Output
Indicates the size of the access. Can be 8, 16, or 32 bits.
Output
Output indicates if the transfer is part of a burst.
Output
Provides information on the access.
Output
32-bit write data bus.
Output
Write not read.
Output
Read data bus.
Output
When HIGH indicates that a transfer has completed on the bus. The signal is
driven LOW to extend a transfer.
Output
The transfer response status. OKAY or ERROR.
Output
32-bit address.
Output
Output indicates the type of the current data transfer. Can be IDLE,
NONSEQUENTIAL, OR SEQUENTIAL.
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AHB Trace Macrocell Interface
Table 16-1 AHB interface ports
16-3
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