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5.6
Tail-chaining
ARM DDI 0337B
Tail-chaining is back-to-back processing of exceptions without the overhead of state
saving and restoration between interrupts. The processor skips the pop of eight registers
and push of eight registers when exiting one ISR and entering another because this has
no effect on the stack contents.
The processor tail-chains if a pending interrupt has higher priority than all stacked
exceptions.
Figure 5-3 shows an example of tail-chaining. If a pending interrupt has higher priority
than the highest-priority stacked exception, the stack push or pop is omitted, and the
processor immediately fetches the vector for the pending interrupt. The ISR that is
tail-chained into starts execution six cycles after exiting the previous ISR.
On return from the last ISR, INTISR[2] is higher priority than any stacked ISR, or other
pended interrupt, and so the processor tailchains to the ISR corresponding to
INTISR[2]. In the cycle that the ISR for INTISR[2] enters execute:
•
ETMINSTAT[2:0] indicates that the ISR has been entered (3'b001). This is a 1
cycle pulse.
•
CURRPRI[7:0] indicates the priority of the active interrupt. CURRPRI remains
asserted throughout the duration of the ISR.
•
ETMINTNUM[8:0] indicates the number of the active interrupt.
ETMINTNUM remains asserted throughout the duration of the ISR.
Figure 5-3 shows that there is a 6-cycle latency from returning from the last ISR to
executing the new ISR.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Exceptions
Figure 5-3 Tail-chaining timing
5-13
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