Table A-6 Dcode Interface - ARM Cortex-M3 Technical Reference Manual

A.6 DCode interface
Name Direction
HADDRD[31:0] Output
HTRANSD[1:0] Output
HWRITED Output
HSIZED[2:0] Output
HBURSTD[2:0] Output
HPROTD[3:0] Output
EXREQD
MEMATTRD[1:0] Output
HWDATAD[31:0] Input
HREADYD Input
HRESPD[1:0] Input
HRDATAD[31:0] Input
EXRESPD Input
ARM DDI 0337B
Table A-6 lists the signals of the DCode interface.
Description
32-bit data address bus
Indicates whether the current transfer is IDLE, NONSEQUENTIAL, or
SEQUENTIAL.
Write not read
Indicates the size of the access. Can be 8, 16, or 32 bits.
Indicates if the transfer is part of a burst. Data accesses are performed as INCR on
Cortex-M3.
Provides information on the access.
Exclusive request.
Memory attributes.
Bit 0 = allocate
Bit 1 = shareable.
Data read bus.
When HIGH indicates that a transfer has completed on the bus. This signal is driven
LOW to extend a transfer.
The transfer response status. OKAY or ERROR.
Read data.
Exclusive response.
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Signal Descriptions

Table A-6 DCode interface

A-7