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5.5
Pre-emption
5.5.1
Stacking
ARM DDI 0337G
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The following sections describe the behavior of the processor when it takes an
exception:
•
Stacking
•
Late-arriving on page 5-15
•
Tail-chaining on page 5-14.
When the processor invokes an exception, it automatically stores the following eight
registers to the SP in the following order:
•
Program Counter (PC)
•
Processor Status Register (xPSR)
•
r0-r3
•
r12
•
Link Register (LR).
The SP is decremented by eight words by the completion of the stack push. Figure 5-1
shows the contents of the stack after an exception pre-empts the current program flow.
Note
•
Figure 5-1 shows the order on the stack.
•
If STKALIGN is set in the Configuration Control Register then an extra word can
be inserted before the stacking takes place. See Configuration Control Register on
page 8-26.
After returning from the ISR, the processor automatically pops the eight registers from
the stack. Interrupt return is passed as a data field in the LR, so ISR functions can be
normal C/C++ functions, and do not require a veneer.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Figure 5-1 Stack contents after pre-emption
Non-Confidential
Exceptions
Old SP
<previous>
PSR
PC
LR
r12
r3
r2
r1
SP
r0
5-11
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