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System Debug
11.4
FPB
11.4.1
FPB programmer's model
11-6
The FPB:
•
implements hardware breakpoints
•
patches code and data from code space to system space.
A full FPB unit contains:
•
Two literal comparators for matching against literal loads from Code space, and
remapping to a corresponding area in System space.
•
Six instruction comparators for matching against instruction fetches from Code
space, and remapping to a corresponding area in System space. Alternatively, you
can individually configure the comparators to return a Breakpoint Instruction
(BKPT) to the processor core on a match, so providing hardware breakpoint
capability.
The FPB contains a global enable, but also individual enables for the eight comparators.
If the comparison for an entry matches, the address is remapped to the address set in the
remap register plus an offset corresponding to the comparator that matched, or is
remapped to a BKPT instruction if that feature is enabled. The comparison happens
dynamically, but the result of the comparison occurs too late to stop the original
instruction fetch or literal load taking place from the Code space. The processor ignores
this transaction however, and only the remapped transaction is used.
If an MPU is present, the MPU lookups are performed for the original address, not the
remapped address.
You can remove the FPB if no debug is required or alternatively the number of
breakpoints it supports can be reduced to two. If the FPB supports only two breakpoints
then only comparators 0 and 1 are used, and flash patching is not supported.
Note
•
Unaligned literal accesses are not remapped. The original access to the DCode
bus takes place in this case.
•
Load exclusives are Unpredictable to the FPB. The address is remapped but the
access does not take place as an exclusive load.
•
Remapping to the bit-band alias directly accesses the alias address, and does not
remap to the bit-band region.
Table 11-1 on page 11-7 lists the flash patch registers.
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