Figure 8-18 Bus Fault Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
Bits Field
[2] -
[1] DACCVIOL
[0] IACCVIOL
8-34
Table 8-22 Memory Manage Fault Status Register bit assignments (continued)
Function
Reserved
Data access violation flag. Attempting to load or store at a location that does not permit the
operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This error
loads MMAR with the address of the attempted access.
Instruction access violation flag. Attempting to fetch an instruction from a location that does
not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region, even
when the MPU is disabled or not present. The return PC points to the faulting instruction. The
MMAR is not written.
Bus Fault Status Register
The flags in the Bus Fault Status Register indicate the cause of bus access faults.
The register address, access type, and Reset state are:
Address
0xE000ED29
Access Read/write-one-to-clear
Reset state
0x00000000
Figure 8-18 shows the bit assignments of the Bus Fault Status Register.
Copyright © 2005-2008 ARM Limited. All rights reserved.

Figure 8-18 Bus Fault Status Register bit assignments

Non-Confidential
7 6 5 4 3 2 1 0
BFARVALID
Reserved
STKERR
UNSTKERR
IMPRECISERR
PRECISERR
IBUSERR
ARM DDI 0337G
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