Table 9-6 Mpu Region Attribute And Size Register Bit Assignments; Figure 9-5 Mpu Region Attribute And Size Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

31
Bits Field Function
[31:29] - Reserved.
[28] XN Instruction access disable bit:
1 = disable instruction fetches
0 = enable instruction fetches.
[27] - Reserved.
[26:24] AP Data access permission field:
Value Privileged permissions
b000 No access
b001 Read/write
b010 Read/write
b011 Read/write
b100 Reserved
b101 Read-only
b110 Read-only
b111 Read-only
[23:22] - Reserved.
[21:19] TEX Type extension field.
[18] S Shareable bit:
1 = shareable
0 = not shareable.
[17] C Cacheable bit:
1 = cacheable
0 = not cacheable.
ARM DDI 0337G
Unrestricted Access
29 28 27 26 24 23 22 21
R
X
Res e AP Res.
N
s

Figure 9-5 MPU Region Attribute and Size Register bit assignments

Table 9-6 describes the bit assignments of the MPU Region Attribute and Size Register.
For more information, see MPU access permissions on page 9-13.

Table 9-6 MPU Region Attribute and Size Register bit assignments

Copyright © 2005-2008 ARM Limited. All rights reserved.
19 18 17 16 15
TEX S C B
User
permissions
No access
No access
Read-only
Read/write
Reserved
No access
Read-only
Read-only.
Non-Confidential
Memory Protection Unit
8 7 6 5
SRD Res.
1 0
E
SIZE N
A
9-9