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Signal Descriptions
A.6
ICode interface
Name
Direction
HADDRI[31:0]
Output
HTRANSI[1:0]
Output
HSIZEI[2:0]
Output
HBURSTI[2:0]
Output
HPROTI[3:0]
Output
MEMATTRI[1:0]
Output
BRCHSTAT[3:0]
Output
HRDATAI[31:0]
Input
HREADYI
Input
HRESPI[1:0]
Input
A-8
Table A-6 lists the signals of the ICode interface.
Description
32-bit instruction address bus
Indicates whether the current transfer is IDLE or NONSEQUENTIAL.
Indicates the size of the instruction fetch. All instruction fetches are 32-bit on
Cortex-M3.
Indicates if the transfer is part of a burst. All instruction fetches and vector table loads
are performed as SINGLE on Cortex-M3.
Provides information on the access. Always indicates cacheable and non-bufferable
on this bus.
HPROTI[0] = 0 indicates instruction fetch
HPROTI[0] = 1 indicates vector fetch
Memory attributes. Always 01 for this bus (non-shareable, allocate).
Provides hint information on the current or coming AHB fetch requests. Conditional
opcodes could be a speculation and subsequently discarded.
0000 No hint
0001 Conditional branch backwards in decode
0010 Conditional branch in decode
0011 Conditional branch in execute
0100 Unconditional branch in decode
0101 Unconditional branch in execute
0110 Reserved
0111 Reserved
1000 Conditional branch in decode taken (cycle after IHTRANS)
1001 ... 1111 Reserved
Instruction read bus.
When HIGH indicates that a transfer has completed on the bus. This signal is driven
LOW to extend a transfer.
The transfer response status. OKAY or ERROR.
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Table A-6 ICode interface
ARM DDI 0337G
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