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Memory Protection Unit
9.5
Updating an MPU region
9.5.1
Updating an MPU region using CP15 equivalent code
9-16
There are three registers consisting of three memory mapped words that program the
MPU regions. These are part registers that you can individually program and access.
This means that you can port existing ARMv6, ARMv7, and CP15 code. This replaces
MRC and MCR with LDRx and STRx operations.
You can also access these registers as three words, and program them using only two
words. Aliases are provided to enable programming a set of regions simultaneously
using an STM instruction.
Using CP15 equivalent code:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
MOV R0,#NVIC_BASE
ADD R0,#MPU_REG_CTRL
STR R1,[R0,#0]; region number
STR R4,[R0,#4]; address
STRH R2,[R0,#8]; size and enable
STRH R3,[R0,#10]; attributes
Note
If interrupts could pre-empt during this period, this region could affect them. This
means that the region must be disabled, written, and then enabled. This is usually not
necessary for a context switcher, but would be necessary if updated elsewhere.
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
MOV R0,#NVIC_BASE
ADD R0,#MPU_REG_CTRL
STR R1,[R0,#0]; region number
BIC R2,R2, #1; disable
STRH R2,[R0,#8]; size and enable
STR R4,[R0,#4]; address
STRH R3,[R0,#10]; attributes
ORR R2,#1; enable
STRH R2,[R0,#8]; size and enable
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