Table 9-6 Mpu Region Attribute And Size Register Bit Assignments; Figure 9-5 Mpu Region Attribute And Size Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

31
Re-
served
Field Name
[31:29] -
[28] XN
[27] -
[26:24] AP
Value
b000
b001
b010
b011
b100
b101
b110
b111
[23:22] -
[21:19] TEX
[18] S
[17] C
ARM DDI 0337B
29 28 27 26 24 23 22 21
R
X
e AP Res.
N
s

Figure 9-5 MPU Region Attribute and Size Register bit assignments

Table 9-6 describes the fields of the MPU Region Attribute and Size Register. For more
information, see MPU access permissions on page 9-13.

Table 9-6 MPU Region Attribute and Size Register bit assignments

Definition
Reserved.
Instruction access disable bit:
1 = disable instruction fetches
0 = enable instruction fetches.
Reserved.
Data access permission field:
Privileged
permissions
no access
read/write
read/write
read/write
reserved
read-only
read-only
read-only.
Reserved.
Type extension field.
Shareable bit:
1 = shareable
0 = not shareable.
Cacheable bit:
1 = cacheable
0 = not cacheable.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
19 18 17 16 15
TEX S C B
User
permissions
no access
no access
read-only
read/write
reserved
no access
read-only
read-only.
Memory Protection Unit
8 7 6 5
SRD Res. REGION SIZE
1 0
E
N
A
9-9