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Embedded Trace Macrocell
15.6
ETM programmer's model
15.6.1
APB interface
15.6.2
List of ETM registers
Name
ETM Control
Configuration Code
Trigger event
ASIC Control
ETM Status
System Configuration
TraceEnable
TraceEnable Event
TraceEnable Control 1
FIFOFULL Region
FIFOFULL Level
15-14
The ETM programmer's model is described in detail in the ARM Embedded Trace
Macrocell Architecture Specification. This section defines the implementation specific
features of the ETM programmer's model.
The ETM contains an Advanced Peripheral Bus (APB) slave interface that can read and
write to the ETM registers. This interface is synchronous to the processor clock, and can
be accessed by the core and the external debug interface through the SW-DP/JTAG-DP.
The ETM registers are listed in Table 15-3. For full details, see the ARM Embedded
Trace Macrocell Architecture Specification.
Type
R/W
RO
WO
WO
RO or R/W
RO
WO
WO
WO
WO
WO or R/W
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Address
Present
Yes
0xE0041000
0xE0041004
Yes
0xE0041008
Yes
0xE004100C
No
0xE0041010
Yes
0xE0041014
Yes
0xE0041018,
No
0xE004101C
0xE0041020
Yes
0xE0041024
Yes
0xE0041028
No
0xE004102C
Yes
Table 15-3 ETM registers
Description
For a description, see page 15-17.
For a description, see page 15-17.
Defines the event that controls the
trigger.
-
Provides information on the
current status of the trace and
trigger logic.
For a description, see page
page 15-17.
-
Describes the TraceEnable
enabling event.
For a description, see page 15-17.
-
Holds the level below which the
FIFO is considered full.
ARM DDI 0337B
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