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Nested Vectored Interrupt Controller
8.1
About the NVIC
8-2
The NVIC:
•
facilitates low-latency exception and interrupt handling
•
controls power management
•
implements System Control Registers.
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256
levels of priority. The NVIC and the processor core interface are closely coupled, which
enables low latency interrupt processing and efficient processing of late arriving
interrupts. The NVIC maintains knowledge of the stacked (nested) interrupts to enable
tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts
in user-mode if you enable the Configuration Control Register (see Configuration
Control Register on page 8-26). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise
stated.
All NVIC registers and system debug registers are little endian regardless of the
endianness state of the processor.
Processor exception handling is described in Chapter 5 Exceptions.
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