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Debug Port
12.3
SW-DP
12.3.1
Clocking
12.3.2
Overview of debug interface
12-20
This section gives an architectural description of the ARM Serial Wire Debug (SW-DP)
interface. In particular, it describes the Serial Wire Debug (SWD) protocol, and how this
protocol provides access to the DP registers. These registers are described in detail in
Debug Port Programmer's Model on page 12-47.
The SW-DP operates with a synchronous serial interface. This uses a single
bi-directional data signal, and a clock signal.
Each sequence of operations on the wire consists of two or three phases:
Packet request
The external host debugger issues a request to the DP. The DP is the
target of the request.
Acknowledge response
The target sends an acknowledge response to the host.
Data transfer phase
This phase is only present if a data read or data write request has been
followed by a valid (OK) acknowledge response, or if the
ORUNDETECT flag is set in the CTRL/STAT Register, see The
Control/Status Register, CTRL/STAT on page 12-53.
The data transfer can be target to host, following a read request, or host
to target, following a write request.
Note
If the Overrun Detect bit is set in the DP CTRL/STAT Register then a data
transfer phase is required on all responses, including WAIT and FAULT.
For details of the CTRL/STAT Register see The Control/Status Register,
CTRL/STAT on page 12-53.
The SW-DP clock, DBGCLK, can be asynchronous to the Cortex-M3 clock.
DBGCLK can be stopped when the debug port is idle. DBGCLK must be clocked for
two additional cycles after the final data bit has been transmitted over the wire.
This section gives an overview of the physical interface used by SW-DP.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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