Table 5-3 Priority Grouping - ARM Cortex-M3 Technical Reference Manual

PRIGROUP[2:0]
b000
b001
b010
b011
b100
b101
b110
b111
ARM DDI 0337B
Table 5-3 shows how writing to PRIGROUP splits an eight bit PRI_N field into a
pre-emption priority field (x) and a subpriority field (y).
Interrupt priority level field, PRI_N[7:0]
Binary point Pre-emption
position field
bxxxxxxx.y [7:1]
bxxxxxx.yy [7:2]
bxxxxx.yyy [7:3]
bxxxx.yyyy [7:4]
bxxx.yyyyy [7:5]
bxx.yyyyyy [7:6]
bx.yyyyyyy [7]
b.yyyyyyyy None
Note
• Table 5-3 shows the priorities for the processor configured with 8 bits of priority.
• For a processor configured with less than eight bits of priority, the lower bits of
the register are always 0. For example, if four bits of priority are implemented,
PRI_N[7:4] sets the priority, and PRI_N[3:0] is 4'b0000.
An interrupt can preempt another interrupt in progress only if its pre-emption priority
is higher than that of the interrupt in progress.
For more information on priority optimizations, Priority Level grouping, and Priority
masking, see the ARMv7-M Architecture Reference Manual.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 5-3 Priority grouping

Number of
Subpriority pre-emption
field priorities
[0] 128
[1:0] 64
[2:0] 32
[3:0] 16
[4:0] 8
[5:0] 4
[6:0] 2
[7:0] 0
Exceptions
Number of
subpriorities
2
4
8
16
32
64
128
256
5-7