Table 2-2 Interrupt Program Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

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Table 2-2 describes the bit assignments of the IPSR.

Table 2-2 Interrupt Program Status Register bit assignments

Execution PSR
The Execution PSR (EPSR) contains two overlapping fields:
• the Interruptible-Continuable Instruction (ICI) field for interrupted load multiple
and store multiple instructions
• the execution state field for the If-Then (IT) instruction, and the Thumb state bit
(T-bit).
Interruptible-continuable instruction field
Load Multiple (LDM) operations and Store Multiple (STM) operations are interruptible.
The ICI field of the EPSR holds the information required to continue the load or store
multiple from the point that the interrupt occurred.
If-then state field
The IT field of the EPSR contain the execution state bits for the If-Then instruction.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Field Name
[31:9] -
[8:0] ISR NUMBER
Non-Confidential
Programmer's Model
Definition
Reserved.
Number of pre-empted exception.
Base level = 0
NMI = 2
SVCall = 11
INTISR[0] = 16
INTISR[1] = 17
.
.
.
INTISR[15] = 31
.
.
.
INTISR[239] = 255
2-7