Table 11-10 Dwt Exception Overhead Count Register Bit Assignments; Figure 11-7 Dwt Exception Overhead Count Register Bit Assignments; Figure 11-8 Dwt Sleep Count Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

31
Bits Field Function
[31:8] - Reserved.
[7:0] EXCCNT Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for
example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow
(every 256 cycles). This counter initializes to 0 when enabled.
Clears to 0 on enabling.
31
ARM DDI 0337G
Unrestricted Access
Access Read-write
Reset state -
Figure 11-7 shows the bit assignments of the DTW Exception Overhead Count
Register.

Figure 11-7 DWT Exception Overhead Count Register bit assignments

Table 11-10 describes the bit assignments of the DWT Exception Overhead Count
Register.

Table 11-10 DWT Exception Overhead Count Register bit assignments

DWT Sleep Count Register
Use the DWT Sleep Count Register to count the total number of cycles during which
the processor is sleeping.
The register address, access type, and Reset state are:
Address
0xE0001010
Access Read-write
Reset state
-
Figure 11-8 shows the bit assignments of the DTW Sleep Count Register.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Reserved
Reserved

Figure 11-8 DWT Sleep Count Register bit assignments

Non-Confidential
System Debug
8 7 0
SLEEPCNT
8 7 0
SLEEPCNT
11-21