Figure 6-1 Reset Signals; Figure 6-2 Power-On Reset - ARM Cortex-M3 Technical Reference Manual

Clocking and Resets
WATCHDOG
6-6
Cortex-M3
SYSRESETn
PORESETn
You must apply power-on or cold reset to the processor when power is first applied to
the system. In the case of power-on reset, the falling edge of the reset signal,
PORESETn, does not have to be synchronous to HCLK. Because PORESETn is
synchronized within the processor, you do not have to synchronize this signal.
Figure 6-2 shows the application of power-on reset. Figure 6-3 on page 6-7 shows the
reset synchronizers within the processor.
HCLK
PORESETn
nTRST
It is recommended that you assert the reset signals for at least three HCLK cycles to
ensure correct reset behavior. Figure 6-3 on page 6-7 shows the internal reset
synchronization.
Copyright © 2005-2008 ARM Limited. All rights reserved.
NVIC
SYSRESETREQ
VECTRESET
NVICDBGRESETn NVICRESETn
Non-Confidential
CM3Core
CORERESETn
System Components
(BusMatrix, MPU)
System Debug
Components
(FPB, DWT, ITM)

Figure 6-1 Reset signals

Figure 6-2 Power-on reset

ARM DDI 0337G
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