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Debug Port
12.1
About the Debug Port
12-2
The processor contains an AHB-AP interface for debug accesses. This interface is
accessed external to the processor by means of a Debug Port (DP) component. The
Cortex-M3 system supports two possible DP implementations:
•
The JTAG Debug Port (JTAG-DP). The JTAG-DP is based on the IEEE 1149.1
Test Access Port (TAP) and Boundary Scan Architecture, widely referred to as
JTAG, and provides a JTAG interface to the AHB-AP port. For more information,
see JTAG-DP on page 12-3,
•
The Serial Wire Debug Port (SW-DP). SW-DP provides a two-pin (clock + data)
interface to the AHB-AP port. For more information, see AHB Access Port on
page 11-35.
These alternative DP implementations provide different mechanisms for debug access
to Cortex-M3. Your implementation might contain either, or both, of these components.
Note
•
Only one DP can be used at once, and switching between the two debug ports
should only be performed when neither DP is in use.
•
Your implementation might contain an additional implementor-specific DP in
parallel to SW_DP or JTAG-DP. See your implementor for details.
For more information on the AHB-AP, see AHB Access Port on page 11-35.
The DP and AP together are referred to as the Debug Access Port (DAP).
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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