Table 10-2 Debug Halting Control And Status Register; Figure 10-1 Debug Halting Control And Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Core Debug
31 30 29 28 27
RAZ
Bits Type
[31:16] Write
[31:26] -
[25] Read
[24] Read
[23:20] -
[19] Read
10-4
26 25 24 23 22 21 20 19 18
DBGKEY
RAZ

Figure 10-1 Debug Halting Control and Status Register bit assignments

Table 10-2 shows the bit functions of the Debug ID Register.
Field Function
DBGKEY Debug Key.
back as status bits [25:16]. If not written as Key, the write operation is
ignored and no bits are written into the register.
- Reserved, RAZ.
S_RESET_ST Indicates that the core has been reset, or is now being reset, since the last
time this bit was read. This a sticky bit that clears on read. So, reading twice
and getting 1 then 0 means it was reset in the past. Reading twice and getting
1 both times means that it is being reset now (held in reset still).
S_RETIRE_ST Indicates that an instruction has completed since last read. This is a sticky
bit that clears on read. This determines if the core is stalled on a load/store
or fetch.
- Reserved, RAZ.
S_LOCKUP Reads as one if the core is running (not halted) and a lockup condition is
present.
Copyright © 2005-2008 ARM Limited. All rights reserved.
17 16 15 14 13 12 11 10
Reserved
Reserved
C_SNAPSTALL
C_MASKINTS
S_REGRDY
C_DEBUGEN
S_HALT
S_SLEEP
S_LOCKUP
S_RETIRE_ST
S_RESET_ST

Table 10-2 Debug Halting Control and Status Register

must be written whenever this register is written. Reads
0xA05F
Non-Confidential
9 8 7 6 5 4 3 2 1 0
Reserved
C_STEP
C_HALT
Write
Read
ARM DDI 0337G
Unrestricted Access