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ARM DDI 0337B
Length
32 bits.
Operating mode
When the IDCODE instruction is the current instruction in the IR, the
shift section of the Device ID Code Register is selected as the serial path
between TDI and TDO:
•
in the Capture-DR state, the 32-bit device ID code is loaded into
this shift section
•
in the Shift-DR state, this data is shifted out, least significant bit
first
•
the shifted-in data is ignored at the Update-DR state.
Order
Figure 12-5 shows the bit order of the Device ID Code Register.
The JTAG DP/AP Access Registers (DPACC/APACC)
The DPACC and APACC scan chains have the same format.
Purpose
Initiate a DP or AP access, to access a DP or AP register. The DPACC and
APACC are used for read and write accesses to registers.
The DPACC is used to access the CTRL/STAT, SELECT and RDBUFF
registers, see JTAG-DP register map on page 12-47.
The APACC is used to access all of the AP registers, see Summary and
description of the AHB-AP registers on page 11-35 for details of
accessing AHB-AP registers, and JTAG-DP Registers on page 12-47 for
details of accessing JTAG-AP registers.
Length
35 bits.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Figure 12-5 JTAG Device ID Code Register bit order
Debug Port
12-11
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