Table 4-2 Memory Region Permissions - ARM Cortex-M3 Technical Reference Manual

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Memory Map
4-4
Table 4-2 shows the permissions of the processor memory regions.
Name
Code
SRAM
SRAM_1M
SRAM_31M
SRAM_bitband
SRAM
Peripheral
Periph_1IM
Periph_31IM
Periph_bit band
Peripheral
External RAM
External RAM
External Device
External Device
System
Private Peripheral
Vendor_SYS
Note
Private Peripheral Bus and System space at
XN. The MPU cannot change this.
For a description of the processor bus interfaces, see Chapter 12 Bus Interface.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Region
0x00000000-0x1FFFFFFF
0x20000000-0x3FFFFFFF
+0000000
+0100000
+2000000
+4000000
0x40000000-0x5FFFFFFF
+0000000
+0100000
+2000000
+4000000
0x60000000-0x7FFFFFFF
0x80000000-0x9FFFFFFF
0xA0000000-0xBFFFFFFF
0xC0000000-0xDFFFFFFF
0xE0000000-0xFFFFFFFF
Bus
+0000000
+0100000
0xE0000000 - 0xFFFFFFFF
Non-Confidential

Table 4-2 Memory region permissions

Device type
Normal
Normal
-
-
Internal
-
Device
-
-
Internal
-
Normal
Normal
Device
Device
-
SO, shared
Device
XN
Cache
-
WT
-
WBWA
-
-
-
-
-
-
-
XN
-
-
-
-
-
-
-
-
-
-
WBWA
-
WT
XN
-
XN
-
XN
-
XN
-
XN
-
are permanently
ARM DDI 0337G
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