Clocking and Resets
6.2
Cortex-M3 resets
Reset input
Description
PORESETn
Resets the entire processor system with the exception of JTAG-DP
SYSRESETn
Resets the entire processor system with the exception of debug logic in the NVIC, FPB, DWT, ITM, and
AHB-AP
nTRST
JTAG-DP reset
6-4
The processor has three reset inputs. These are described in Table 6-3.
Note
nTRST resets JTAG-DP. If your implementation doesn't contain JTAG-DP, this reset
must be tied off.
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Table 6-3 Reset inputs
ARM DDI 0337B