Table 5-11 Debug Faults - ARM Cortex-M3 Technical Reference Manual

Fault
Internal halt request
Breakpoint
Watchpoint
Divide by zero
Unaligned access
External
5.12.3 Fault status registers and fault address registers
ARM DDI 0337B
Table 5-11 shows debug faults.
Flag Notes
HALTED NVIC request from step, core halt, etc.
BKPT SW breakpoint from patched instruction or FPB
DWTTRAP Watchpoint match in DWT
DIVBYZERO Divide by zero when enabled for trap
UNALIGNED Unaligned access when enabled for trap
EXTERNAL EDBGRQ line asserted
Each fault has a fault status register with a flag for that fault.
There are:
• three configurable fault status registers that correspond to the three configurable
fault handlers
• one hard fault status register
• one debug fault status register.
Depending on the cause, one of the five status registers has a bit set.
There are two Fault Address Registers (FAR):
• Bus Fault Address Register (BFAR)
• Memory Fault Address Register (MFAR).
A flag in the corresponding fault status register indicates when the address in the fault
address register is valid.
Note
BFAR and MMFAR are the same physical register. Because of this the BFARVALID
and MMFARVALID bits are mutually exclusive.
Table 5-12 on page 5-30 shows the fault status registers and two fault address registers
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Exceptions

Table 5-11 Debug faults

Trap enable bit
-
-
-
-
-
-
5-29