Table 11-23 Itm Integration Write Register Bit Assignments; Table 11-24 Itm Integration Read Register Bit Assignments; Figure 11-16 Itm Integration Read Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

System Debug
31
11-36
Table 11-23 describes the bit assignments of the ITM Integration Write Register.
Note
Bit [0] drives ATVALIDM when mode is set.
ITM Integration Read Register
Use this register to read the value on ATREADYM
Figure 11-16 shows the ITM Integration Read Register bit assignments.
Table 11-24 describes the bit assignments of the ITM Integration Read Register.
ITM Integration Mode Control Register
Use this register to enable write accesses to the Control Register.
Copyright © 2005-2008 ARM Limited. All rights reserved.

Table 11-23 ITM Integration Write Register bit assignments

Bits Field
[31:1] -
[0] ATVALIDM
Reserved

Figure 11-16 ITM Integration Read Register bit assignments

Table 11-24 ITM Integration Read Register bit assignments

Bits
[31:1]
[0]
Non-Confidential
Function
Reserved
When the integration mode is set:
0 = ATVALIDM clear
1 = ATVALIDM set.
ATREADYM
Field Function
- Reserved
ATREADYM Value on ATREADYM
1 0
ARM DDI 0337G
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