Table 11-20 Itm Trace Enable Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

System Debug
Bits
[31:0]
11-32
ITM Stimulus Ports 0-31
Each of the 32 stimulus ports has its own address. A write to one of these locations
causes data to be written into the FIFO if the corresponding bit in the Trace Enable
Register is set. Reading from any of the stimulus ports returns the FIFO status in bit [0]:
• 0 = full
• 1 = not full.
The polled FIFO interface does not provide an atomic read-modify-write, so you must
use the Cortex-M3 exclusive monitor if a polled printf is used concurrently with ITM
usage by interrupts or other threads. The following polled code guarantees stimulus is
not lost by polled access to the ITM:
; r0 = Value to write to port
; r1 and r2 = Temporary scratch registers
MOV r1, #0xE0000000
Retry LDREX r2, [r1, #Port*4] ; Load FIFO full status
CMP r2, #0
ITT NE
STREXNE r2, [r1, #Port*4]; Try sending value to port
CMPNE r2, #1
BEQ Retry
ITM Trace Enable Register
Use the Trace Enable Register to generate trace data by writing to the corresponding
stimulus port.
The register address, access type, and Reset state are:
Access Read/write
Address 0xE0000E00
Reset
0x00000000
Table 11-20 describes the field of the ITM Trace Enable Register.
Field Function
STIMENA Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port.
Copyright © 2005-2008 ARM Limited. All rights reserved.
; r1 = Stimulus port base
; Compare with full
; If (not full)
; and check for failure
; If full or failed then retry

Table 11-20 ITM Trace Enable Register bit assignments

Non-Confidential
ARM DDI 0337G
Unrestricted Access