Figure 7-5 Pmu, Wic, And Cortex-M3 Interconnect - ARM Cortex-M3 Technical Reference Manual

PMU
ISOLATEn
RETAINn
PWRDOWN
SLEEPHOLDREQPMUn
SLEEPHOLDACKPMUn
SLEEPDEEP
WAKEUP
WICENREQ
WICENACK
ARM DDI 0337G
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INTERRUPTS
WICINT
WAKEUP
WICENREQ
WICENACK
WICSENSE
The non-clocked circuitry can use the signals out of the WIC to deduce whether a
particular interrupt causes the WIC to generate a WAKEUP request, and to provide
alternative power reduction methods not supported by the WIC directly. All WIC
interrupt related pins are agnostic as to how many, or what combinations of INTISR,
NMI, or RXEV are attached as long as the same offset is used throughout the WIC.
The WIC can be disabled by using WICDISABLE, which is a signal indicating that
WIC-based SLEEPDEEP must not be entered, or if it has already been entered, that
WAKEUP be driven high and the SLEEPDEEP policy revert to non-WIC-based. A
debugger must hold this signal high when attached to the system to prevent power
isolation during debug.
The sources and causes of wake-up events are implementation defined and the
implementation can support any number of signals from two and greater. This enables
maximum flexibility over which set of NMI, debug request, interrupts, and RXEV are
used as potential wake-up sources.
Copyright © 2005-2008 ARM Limited. All rights reserved.
CLAMPS
WIC
WICPEND
WICLOAD
WICCLEAR
WICMASK
WICDSREQn
WICDSACKn

Figure 7-5 PMU, WIC, and Cortex-M3 interconnect

Non-Confidential
Power Management
0
OR
Cortex-M3
0
SLEEPHOLDREQn
0
SLEEPHOLDACKn
0
SLEEPDEEP
0 INTISR/NMI/RXEV
0
WICLOAD
0 WICCLEAR
0 WICMASK
0
WICDSREQn
0
WICDSACKn
7-9