Table 17-8 Formatter And Flush Status Register Bit Assignments; Figure 17-6 Formatter And Flush Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Trace Port Interface Unit
31
17-12
Figure 17-6 shows the bit assignments of the Formatter and Flush Status Register.

Figure 17-6 Formatter and Flush Status Register bit assignments

Table 17-8 describes the bit assignments of the Formatter and Flush Status Register.

Table 17-8 Formatter and Flush Status Register bit assignments

Formatter and Flush Control Register
The Formatter and Flush Control Register.
The register address, access type, and Reset state are:
Address
0xE0040304
Access Read/write
Reset state
0x102
Figure 17-7 on page 17-13 shows the bit assignments of the Formatter and Flush
Control Register.
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Reserved
Bits Field
[31:4] -
[3] FtNonStop
[2] TCPresent
[1] FtStopped
[0] FlInProg
4 3 2 1 0
FtNonStop
TCPresent
FtStopped
FlInProg
Function
Reserved
Formatter cannot be stopped
This bit always reads zero
This bit always reads zero
This bit always reads zero
ARM DDI 0337G