Table 11-19 Bit Functions Of The Itm Trace Enable Register - ARM Cortex-M3 Technical Reference Manual

System Debug
Field Name
[31:0] STIMULUS MASK
11-28
ITM Stimulus Ports 0-31
Each of the 32 stimulus ports has its own address. A write to one of these locations
causes data to be written into the FIFO if the corresponding bit in the Trace Enable
Register is set. Reading from any of the stimulus ports returns the FIFO status (0 = Full,
1 = not Full) in bit 0.
The polled FIFO interface does not provide an atomic read-modify-write, so the
Cortex-M3 exclusive monitor must be used if a polled printf is used concurrently with
ITM usage by interrupts or other threads. The following polled code guarantees
stimulus is not lost by polled access to the ITM:
; Cortex-M3 exclusive monitor cleared by interrupt
; R0 = FIFO-full/exclusive status
; R1 = base of ITM stimulus ports
; R2 = value to write
retry
LDREX R0, [R1, #??]
CBZEQ R0, retry
STREX R0, R2, [R1, #??] ; store if FIFO !Full and excl lock
CZBNE R0, retry
ITM Trace Enable Register
Use the Trace Enable Register to generate trace data by writing to the corresponding
stimulus port.
The register address, access type, and Reset state are:
Access Read/write
Address
0xE0000E00
Reset
0x00000000
Table 11-19 describes the fields of the ITM Trace Enable Register.
Definition
Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
; read FIFO status and request excl lock
; FIFO not ready, try again
; excl lock failed, try again

Table 11-19 Bit functions of the ITM Trace Enable Register

ARM DDI 0337B