Figure 9-2 Mpu Control Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

ARM DDI 0337B
Unless HFNMIENA is set, the MPU is not enabled when the exception priority is –1 or
–2. These priorities are only possible when in Hard fault, NMI, or when FAULTMASK
is enabled. The HFNMIENA bit is used to enable the MPU when operating with these
two priorities.
The register address, access type, and Reset state are:
Address
0xE000ED94
Access Read/write
Reset state
0x00000000
Figure 9-2 shows the fields of the MPU Control Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Figure 9-2 MPU Control Register bit assignments

Memory Protection Unit
9-5