Table 11-2 Flash Patch Control Register Bit Assignments; Figure 11-2 Flash Patch Control Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

System Debug
Name
CID1
CID2
CID3
31
Bits Field
[31:15] -
[14:12] NUM_CODE2
[11:8] NUM_LIT
11-8
Type
Read-only
Read-only
Read-only
Flash Patch Control Register
Use the Flash Patch Control Register to enable the flash patch block.
The register address, access type, and Reset state are:
Address
0xE0002000
Access Read/write
Reset state Bit [0] (ENABLE) is reset to 1'b0.
Figure 11-2 shows the bit assignments of the Flash Patch Control Register.
Reserved
Table 11-2 describes the bit assignments of the Flash Patch Control Register.
Function
Reserved. Read As Zero. Write Ignored.
Number of full banks of code comparators, sixteen comparators per bank. Where less than
sixteen code comparators are provided, the bank count is zero, and the number present
indicated by NUM_CODE. This read only field contains 3'b000 to indicate 0 banks for
Cortex-M3 processor.
Number of literal slots field. This read only field contains either b0000 to indicate there are
no literal slots or b0010 to indicate that there are two literal slots.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Table 11-1 FPB register summary (continued)
Address Description
Value
0xE0002FF4 0xE0
Value
0xE0002FF8 0x05
Value
0xE0002FFC 0xB1
14 13
NUM_CODE2

Figure 11-2 Flash Patch Control Register bit assignments

Table 11-2 Flash Patch Control Register bit assignments

Non-Confidential
12 11 8 7
NUM_LIT NUM_CODE1
Reserved
KEY
ENABLE
ARM DDI 0337G
4 3 2 1 0
Unrestricted Access