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12.3.4
Protocol description
ARM DDI 0337B
Protocol error sequence
A protocol error occurs when a host issues a packet request but the target fails to return
any acknowledge response. This is illustrated in Figure 12-12.
Figure 12-12 Serial Wire Debug protocol error after a packet request
This section provides additional information on the DAP Serial Wire Debug operations
that were introduced in Overview of protocol operation on page 12-22.
Connection sequence
A connection sequence is used to ensure that hot-plugging does not result in
unintentional transfers. To ensure that the SW-DP is correctly synchronized to the
header that is used to signal a connection, a wire reset sequence of 50 clock cycles must
be sent first. After the host has transmitted a reset sequence to the SW-DP, a valid header
request for a read of the ID register is accepted, and the normal response and data
returned. Having the host make an ID Code Register read to exit the training state
ensures a high level of confidence that correct packet frame alignment has been
achieved.
The OK response
When it receives a packet request from the debug host, the SW-DP must respond
immediately. It issues an OK response, indicated by an acknowledge phase of b001, if
it is ready for the data phase of the transfer, if one is required.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Debug Port
12-27
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