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7.2
System power management
Sleep mechanism
Sleep-now
Sleep-on-exit
Deep-sleep
a. The WFI instruction can complete even if no exception becomes active. Do not use it to detect the occurrence of an exception.
WFI is normally used in an idle loop in the Thread Mode. For more information on WFI, WFE, BASEPRI, and PRIMASK see
the ARMv7-M Architecture Reference Manual.
ARM DDI 0337B
Writing to the System Control Register (see System Control Register on page 8-23)
controls the Cortex-M3 system power states. Table 7-1 shows the supported sleep
modes.
Description
The Wait For Interrupt (WFI) or the Wait For Event (WFE) instructions request the sleep-now
model. These instructions cause the NVIC to put the processor into the low-power state pending
a
another exception.
When the SLEEPONEXIT bit of the System Control Register is set, the processor enters the
low-power state as soon as it exits the lowest priority ISR. The processor enters the low-power
state without popping registers and a following exception is taken without having to push
registers. The core stays in sleep state until another exception is pended. This is an automated
WFI mode.
Note
Sleep-on-exit might return to base under various situations such as debug. Therefore, base code
must be provided such as an idle loop or idle thread.
Deep-sleep is used in conjunction with Sleep-now and Sleep-on-exit. When the SLEEPDEEP bit
of the System Control Register is set, the processor indicates to the system that deeper sleep is
possible.
The processor exports the following signals to indicate when the processor is sleeping:
SLEEPING This signal is asserted when in Sleep-now or Sleep-on-exit modes, and
indicates that the clock to the processor can be stopped. On receipt of a
new interrupt, the NVIC de-asserts this signal, releasing the core from
sleep. An example of SLEEPING usage is shown in SLEEPING on
page 7-4.
SLEEPDEEP
This signal is asserted when in Sleep-now or Sleep-on-exit modes when
the SLEEPDEEP bit of the System Control Register is set. This signal is
routed to the clock manager and can be used to gate the processor and
system components including the Phase Locked Loop (PLL) to achieve
greater power savings. On receipt of a new interrupt, the Nested Vectored
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Power Management
Table 7-1 Supported sleep modes
7-3
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